Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBS, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
In a complementary metal oxide (“CMOS”) configured IOB, a buffer conventionally is of a “push-pull” configuration. A push-pull configuration is where a p-channel transistor is coupled in series with an n-channel transistor, usually between power and ground, to either push current from a power terminal into a middle node or pull current from the middle node into the ground terminal. Unfortunately, p-type transistors and n-type transistors may not have the same resistivity. This can cause asymmetry between rise and fall times for going from a high logic level voltage to a low logic level voltage and vice versa. Moreover, this asymmetry in resistivity of n-type and p-type transistors is not only semiconductor process dependent, but is subject to change due to changes in environmental conditions, especially extreme temperatures.
To compensate for differences between n-type and p-type transistor resistivity, others have created a digitally controlled impedance buffer. In a digitally controlled impedance buffer a different number of p-channel and n-channel transistors are selected in order to compensate for asymmetry in rise and fall time output waveforms from a buffer.
A limitation of CMOS is needed voltage levels. For example, CMOS voltage separation of 1.5 volts between power and ground conventionally requires an input voltage of no more than 0.2 volts to read a logic 0 and no less than 1.3 volts to read a logic 1. Thus, there is a certain time consumed in going from high to low or low to high voltage levels, or what is known as going “rail-to-rail”.
In order to achieve high data rates, such as approximately two hundred megabits per second and greater, others have implemented high-speed interfaces. Examples of such interfaces include high-speed transceiver logic (HSTL) and stubs series transceiver logic (SSTL), among others. HSTL and SSTL both use parallel termination. In order to avoid reflection of signals caused by an impedance mismatch between an FPGA output and a printed circuit board (PCB) to which such an FPGA was attached, parallel termination resistors were needed.
However, it is possible to operate a narrow voltage swing for a higher resulting data rate in one direction, for example, unidirectionally from a digitally controlled impedance buffer driver to an HSTL receiver over a link, without parallel termination resistance. This approach requires two unidirectional links to provide the bi-directional communication. This approach therefore uses additional dedicated traces, as well as additional input and output pins, as compared with a single bi-directional communication link. It is also possible to operate a single bi-directional communication link with narrow voltage swings with bi-directional IOBs using parallel termination resistance.
Parallel termination resistance, though reducing reflection of an output from an integrated circuit, introduced negative effects, namely, signal attenuation. Notably, signal attenuation limits the degree to which CMOS voltage levels may be reduced and still meet narrow voltage swing thresholds. Sometimes, conventional parallel termination for a bi-directional communication link is done externally to an integrated circuit, and thus an integrated circuit attached to a PCB would have to have an external resistance matched to the transmission line impedance for each I/O pin. Moreover, conventional CMOS drivers that are not adjustable for n-channel and p-channel transistor selection for impedance trimming conventionally exhibit asymmetrical signal rise and fall times. This asymmetry causes duty cycle distortion and can limit the data rate at which a link can effectively operate. Schultz et al. in U.S. patent application Ser. No. 09/684,539 describe a “Digitally Controlled Impedance for I/O of an Integrated Circuit Device” in which impedance is digitally controlled and matched to an external impedance, but in which no external terminal resistors are used. But the disadvantages of termination resistance are still present.
Accordingly, it would be both desirable and useful to provide an IOB that allows operation in a bi-directional mode that does not suffer from limitations associated with parallel termination resistance. Moreover, it would be further desirable and useful if such an IOB did not need external or internal parallel termination resistance.